The present invention relates to a multiport DRAM (Dynamic Random Access Memory).
FIG. 4 shows a configuration of a dual port DRAM as an example of prior art multiport DRAMs. This multiport DRAM includes a RAM (Random Access Memory) section 5 for implementing random access operation, a data transfer gate section 6 for controlling data transfer from the RAM section, and a SAM (Serial Access Memory) section 7 for implementing serial access operation.
The RAM section 5 is composed of a first RAM 5A in which the MSB (Most Significant Bit) of the column address is "0" and a second RAM 5B in which the MSB of the column address is "1". Furthermore, the data transfer gate section 6 is composed of a first transfer gate 6A and a second transfer gate 6B, so as to correspond to the two RAMs. The SAM section 7 is composed of a first data register 7C, a second register 7D, and an input/output buffer 8.
In the above-mentioned configuration, data are written to or read from the RAM section 5 in the same way as in an ordinary DRAM. In the case of the data write operation, a data inputted from external through an I/O buffer 2 is written to a memory cell of the RAM section 5 whose address corresponds to an address signal inputted through an address buffer 1. In this operation, the address signal is transmitted to a column address decoder 3 and a row address decoder 4 via the address buffer 1 for decoding, and a memory cell whose row and column correspond to the decoded address is selected.
Data are transferred from the RAM section 5 to the SAM section 7 as follows: first, data stored in a row of the RAM section 5A, for instance are transmitted to the data register 7C of the SAM section 7 through the transfer gate 6A. In more detail, as shown in FIG. 5, when one word line (e.g., WL.sub.i) is selected, data are read from the memory cells connected to the word lines WL.sub.i of the respective blocks a.sub.1, a.sub.2, a.sub.3, a.sub.4 of the RAM 5A to the respective bit line BL.sub.0j (j=1, 2, . . . n); these read data are amplified by sense amplifiers SA.sub.01, SA.sub.02, SA.sub.03, SA.sub.04 ; and the read data are outputted to the bit line BL.sub.0j after amplification. In this operation, when a control signal for turning on the transfer gate 6A is transmitted to a control line CL, the transfer gate 6A is turned on; the amplified data are transferred to the respective blocks c.sub.1, c.sub.2, c.sub.3, c.sub.4 of the data register 7C; and then the read data are stored in the respective blocks when the transfer gate 6A is turned off. Each block of the data register 7C is composed of a flip-flop composed of two P-channel transistors and two N-channel transistors, and a DQ (input/output) gate 14. The P-channel transistors of the flip-flop are connected to the D.sub.1 line and the N-channel transistors of the flip-flop are connected to the D.sub.2 line, respectively. A drive potential V.sub.cc is applied to one of these D.sub.1 and D.sub.2 lines and zero potential is applied to the other of these lines. Furthermore, in FIG. 5, each block of the data register 7C of the SAM section 7 is connected to a pair of bit line BL.sub.0j and bit line BL.sub.0j through the respective transfer gates 6A. However, there exists another type in which one end of each block c'.sub.j is connected to one of a pair of the bit lines (e.g., bit line BL.sub.0j) via a transfer gate 6A; and the transferred data are inverted through a NOT gate 60 before the transferred data are stored, as shown in FIG. 6.
As described above, after data have been transferred from the RAM 5A to the data register 7C, when the DQ gate 14 of the SAM section 7 is turned on (see FIG. 5), the data transferred to the data register 7C are outputted to the outside via the output/input buffer 8 of the SAM section 7 (see FIG. 4). During this data output operation, the data stored in a row of the RAM 5B are transferred to the data register 7D through the transfer gate 6B in the same way as described already. Furthermore, when the data transmitted to the data register 7D are being outputted to the outside through the input/output buffer 8, the data stored in a row of the RAM 5A are transferred to the data register 7C through the transfer gate 6A. By repeating the above-mentioned operation, necessary data stored in RAM section 5 are outputted to the outside through the SAM section 7 (see FIG. 5). Further, data can be transferred from the SAM section 7 to the RAM section 5 by implementing the above-mentioned procedure in reverse order.
As described above, in the prior art multiport DRAM, as shown in FIG. 5, since the RAM block (e.g., block a.sub.i (i=1, 2, . . .)) and the block c.sub.i of data register 7C are arranged so as to correspond to each other one by one, as shown in FIG. 7, the data stored in the RAM 5A are fixedly transferred to the data register 7C and the data stored in the RAM 5B are fixedly transferred to the data register 7D, respectively. Accordingly, when data are required to be read from the SAM section 7 in series fashion, after data stored in one of the data registers 7C and 7D have been read, data stored in the other thereof are further read. In other words, data stored on the RAM 5A side and the RAM 5B side are inevitably read alternately.
As described above, in the prior art multiport DRAM, it is impossible to continuously read data stored on only the RAM 5A side or the RAM 5B side. In the same way, it is impossible to continuously write data to only the RAM 5A side or the RAM 5B side.